1. Field of the Invention
The present invention relates to a liquid crystal display thin film transistor array and a method of fabricating the same and, more particularly, to the structure of an active matrix liquid crystal display thin film transistor array which can prevent disconnection of a bus line and can be fabricated without increasing the number of conventional fabrication steps, and a method of fabricating the same.
2. Description of the Prior Art
Nowadays, with the rapid progress of an information-aligned society, flat displays replacing CRTs (Cathode Ray Tubes) have become important devices for extending the multimedia market as interfaces from various information terminals such as computers to human beings.
As flat displays, liquid crystal displays and plasma displays are promising. In particular, liquid crystal displays are developing the market with the spread of notebook personal computers and small information terminals. Of liquid crystal displays, active matrix liquid crystal displays have high display quality with high contrast on the entire screen because there is no crosstalk, compared to simple matrix liquid crystal displays such as STN displays. Therefore, active matrix liquid crystal displays have attracted attention not only as displays of small personal computers but also as view-finders of video cameras, projectors, and flat television sets.
In a liquid crystal display, a liquid crystal material is sandwiched between two electrodes having aligned surfaces, and an electric field is applied to a liquid crystal by applying a voltage to these electrodes. Consequently, the directions of liquid crystal molecules are controlled by this electric field, and the deflecting direction of light is modulated. In this manner, ON and OFF of light are controlled. As this liquid crystal material, a TN (Twisted Nematic) liquid crystal is often used.
Most recent active matrix liquid crystal displays operate in a normally white mode in which white is displayed by transmitting light when no electric field is applied between the two electrodes and black is displayed by transmitting no light when an electric field is applied. As an element for driving liquid crystal, a thin film transistor (to be referred to as a TFT hereinafter) having high response speed and high display quality is generally used.
An outline of the arrangement of a conventionally used active matrix liquid crystal display will be described below with reference to FIGS. 1 and 2.
FIG. 1 shows the basic arrangement of a TFT array of this conventional active matrix liquid crystal display. Referring to FIG. 1, a plurality of gate bus lines (scan lines) A1, A2, . . . , Am and a plurality of drain bus lines (signal lines) S1, S2, . . . , Sn are arranged in a matrix manner on a TFT substrate (not shown). TFTs C11, C12, . . . , Cmn are formed at the intersections of these gate bus lines and drain bus lines.
FIG. 2 shows an equivalent circuit of one pixel in the TFT array of the active matrix liquid crystal display shown in FIG 1. As shown in FIG 2, a gate G and a drain D of the TFT Cmn are connected to the gate bus line Am and the drain bus line Sn, respectively. A source S as the third electrode of the TFT Cmn is connected to a pixel electrode 116.
As described above, each TFT is selected by a gate bus line and a drain bus line, and an image signal voltage is written in the display pixel. In this manner, a desired image is displayed.
As one example of common active matrix TFT array structures, a structure and a method of fabricating the structure disclosed in Japanese Examined Patent Publication No. 4-52925 will be described below with reference to FIGS. 3, 4A to 4F, and 5A to 5F. FIG. 3 is a plan view showing the arrangement of electrodes and interconnections of one element in this conventional TFT array. FIGS. 4A to 4F and 5A to 5F are sectional views showing a process of fabricating sections taken along lines IV--IV and V--V, respectively, in FIG. 3 in order of fabrication steps.
The process of fabricating this conventional TFT array will be described below with reference to FIGS. 3, 4A to 4F, and 5A to 5F. First, as shown in FIGS. 4A and 5A, a gate bus line 101 made of a metal film of, e.g., Cr, Al, Ta, or Mo and a gate electrode 102 are patterned into predetermined shapes on a transparent insulating substrate 100 such as a glass substrate.
As shown in FIGS. 4B and 5B, an insulating layer a (gate oxide film) 103 made of a material such as a silicon oxide film or a silicon nitride film is formed. Additionally, a channel layer 104 made from intrinsic semiconductor amorphous silicon (to be referred to as "a-Si(I)" hereinafter) and a contact layer 105 made from n-type semiconductor amorphous silicon (to be referred to as "a-Si(n.sup.+)" hereinafter) are formed in this order on the insulating layer a 103.
As shown in FIG. 4C, the channel layer 104 and the contact layer 105 are patterned. After that, a portion of the insulating layer a 103 is removed by patterning from the surface of the metal film of, e.g., Cr, Al, Ta, or Mo in a peripheral terminal portion (not shown) for mounting an external driving circuit for applying a signal to the gate bus line 101 and a drain bus line 106 (to be formed later).
Next, as shown in FIG. 4D, a pixel electrode 110 is patterned into a predetermined shape by using a transparent conductive material such as ITO.
Additionally, as shown in FIGS. 4E and 5E, the drain bus line 106, a drain electrode 107, and a source electrode 108 are patterned into predetermined shapes by using a metal film of, e.g., Cr, Al, Ta, or Mo in the same manner as the gate bus line 101 and the gate electrode 102. In this patterning, the source electrode 108 is so formed as to be electrically connected to the pixel electrode 110. To separate the drain electrode 107 from the source electrode 108, an unnecessary portion of the contact layer 105 on the channel layer 104 is etched away.
After that, as shown in FIGS. 4F and 5F, an insulating layer b (insulating interlayer) 109 made of a material such as a silicon nitride film is formed. A portion of this insulating layer b 109 is removed by patterning from the surface of the metal film of, e.g., Cr, Al, Ta, or Mo in the peripheral terminal portion (not shown) for mounting the external driving circuit for applying a signal to the gate bus line 101 and the drain bus line 106. In this way, a TFT array substrate is completed. In this TFT array substrate, the gate bus line 101 and the drain bus line 106 are insulated from each other by the insulating layer a 103.
In the conventional TFT array substrate obtained as described above, the drain bus line 106 and the pixel electrode 110 are formed on the same layer. Therefore, to prevent a short circuit, the drain bus line 106 and the pixel electrode 110 cannot be made close to each other. This makes it impossible to increase the aperture ratio (the ratio of an area which transmits light to the display area of the liquid crystal display). Additionally, a metal foreign matter or a pattern residue formed when the drain bus line 106 or the pixel electrode 110 is patterned short-circuits the drain bus line 106 and the pixel electrode 110. This results in a point defect.
Although not shown in the above prior art, as a method of preventing disconnection of the drain bus line 106, a transparent conductive film can also be formed below the drain bus line 106 by using the same material as the pixel electrode 110 when the pixel electrode 110 is formed. This two-layered drain bus line is also well known as one prior art. Even in this prior art, however, the drain bus line 106 and the pixel electrode 110 are formed on the same layer. Accordingly, the aperture ratio cannot be increased, and point defects readily occur.
Japanese Unexamined Patent Publication No. 6-130416 has disclosed an example of the structure of an active matrix TFT array for solving the problems of the above prior art explained with reference to FIGS. 3, 4A to 4F, and 5A to 5F. In the structure disclosed in Japanese Unexamined Patent Publication No. 6-130416, a storage capacitance electrode is separately formed. However, in the present invention to be described later, this storage capacitance electrode is formed on a gate bus line 101. For descriptive consistency, therefore, the drawings of the structure disclosed in Japanese Unexamined Patent Publication No. 6-130416 are slightly changed in the following explanation. The structure of this prior art and a method of fabricating the structure will be described below with reference to FIGS. 6, 7A to 7F, and 8A to 8F. FIG. 6 is a plan view showing the arrangement of electrodes and interconnections of one element in this conventional TFT array. FIGS. 7A to 7F and 8A to 8F are sectional views showing a process of fabricating sections taken along lines VII--VII and VIII--VIII, respectively, in FIG. 6 in order of fabrication steps.
The conventional TFT array shown in FIGS. 6, 7A to 7F, and 8A to 8F can be fabricated by the same process as explained above with reference to FIGS. 3, 4A to 4F, and 5A to 5F until the step of removing a portion of an insulating layer a 103 by patterning from the surface of a metal film of, e.g., Cr, Al, Ta, or Mo in a peripheral terminal portion (not shown) for mounting an external driving circuit for applying a signal to a gate bus line 101 and a drain bus line 106 (to be formed later), i.e., until the step shown in FIGS. 7C and 8C. Therefore, its detailed description will be omitted.
Next, as shown in FIGS. 7D and 8D, a 100- to 300-nm thick metal film of, e.g., Cr, Al, Ta, or Mo is formed by sputtering and patterned into a predetermined shape to form the drain bus line 106, a drain electrode 107, and a source electrode 108. Additionally, to divide a contact layer 105 into a portion on the drain electrode 107 side and a portion on the source electrode 108 side, an unnecessary portion of the contact layer 105 on the channel layer 104 is etched away.
After that, as shown in FIGS. 7E and 8E, to form an insulating layer b (insulating interlayer) 109 for separating the drain bus line 106 from a pixel electrode 110 (to be formed later), a 100- to 400-nm thick silicon nitride film is formed by plasma CVD using silane and ammonia gas as main constituents. A contact hole a 113 for electrically connecting the source electrode 106 to the pixel electrode 110 is then patterned into a predetermined shape.
Next, as shown in FIG. 7F, a film is formed by sputtering by using a transparent conductive film such as ITO, patterned into a predetermined shape, and etched to form the pixel electrode 110. In this way, a TFT array substrate is completed. In this TFT substrate, the gate bus line 101, the drain bus line 106, and the pixel electrode 110 are insulated from each other by the insulating layer a 103 and the insulating layer b 109.
In the TFT array substrate obtained as described above, compared to the prior art shown in FIGS. 3, 4A to 4F, and 5A to 5F, the pixel electrode 110 can be extended to a region above the drain bus line 106. This makes this TFT array substrate superior to the first prior art. That is, the aperture ratio can be increased, and a point defect resulting from a short circuit of the drain bus line 106 and the pixel electrode 110 can be prevented because the drain bus line 106 is isolated from the pixel electrode 110 by the insulating layer b 109.
Unfortunately, the prior art shown in FIGS. 6, 7A to 7F, and 8A to 8F has the problem that the drain bus line 106 is easily disconnected because of its single-layered structure. More specifically, the drain bus line 106 at the intersection of the gate bus line 101 and the drain bus line 106 has a single-layered structure. Accordingly, when the drain bus line 106 is etched, a solution such as ammonium ceric nitrate permeates from the step portion and etches the metal pattern, or the drain bus line 106 cracks from the step portion. This results in a line defect which is a fatal defect for a liquid crystal display.
The structure of a TFT array disclosed in Japanese Unexamined Patent Publication No. 1-105575 is one counter-measure against a drain line defect as the problem of the prior art explained with reference to FIGS. 6, 7A to 7F, and 8A to 8F. As another example of the common active matrix TFT array structures, the structure and a method of fabricating the structure disclosed in Japanese Unexamined Patent Publication No. 1-105575 will be described below with reference to FIGS. 9, 10A to 10G, and 11A to 11G. FIG. 9 is a plan view showing the arrangement of electrodes and interconnections of one element in this conventional TFT array. FIGS. 10A to 10G and 11A to 11G are sectional views showing a process of fabricating sections taken along lines X--X and XI--XI in FIG. 9 in order of fabrication steps.
The process of fabricating this conventional TFT array will be described below with reference to FIGS. 9, 10A to 10G, and 11A to 11G. First, as shown in FIGS. 10A and 11A, a gate bus line 101 made of a Ti layer and a gate electrode 102 are formed on a transparent insulating substrate 100 such as a glass substrate.
As shown in FIGS. 10B and 11B, an insulating layer a (gate oxide film) 103 made of a material such as a silicon nitride film is formed.
Additionally, as shown in FIGS. 10C and 11C, a channel layer 104 made from intrinsic semiconductor amorphous silicon (to be referred to as "a-Si(I)" hereinafter), a silicon oxide film (not shown) as a protective film, and a contact layer (not shown) are formed on the insulating layer a 103 by chemical vapor deposition (P-CVD). Subsequently, a resist pattern for forming a self-aligned transistor is formed and used as a mask to etch the channel layer 104 and the silicon oxide film.
After that, as shown in FIGS. 10D and 11D, a contact layer 105 made from a-Si(n.sup.+) and Ti and Al layers as metal films for forming drain and source electrodes are formed. A resist film having a pattern for forming a drain electrode 107 and a source electrode 108 is formed and used as a mask to etch the Al layer, Ti layer, and contact layer 105.
Next, as shown in FIGS. 10E and 11E, the resist is removed, and polyimide serving as an insulating interlayer b 109 is formed. A resist film having a pattern which exposes a contact hole b 114 for the drain electrode 107 and the source electrode 108 is formed. Gas-plasma etching is performed by using this resist as a mask to pattern the insulating interlayer b 109.
As shown in FIGS. 10F and 11F, an ITO layer as a transparent conductive film is formed. An unnecessary portion of this ITO layer is removed by a lift-off method to form an ITO layer 112 for bridging a pixel electrode 110 and the drain electrode 107.
After that, as shown in FIGS. 10G and 11G, a Cr layer and an Al layer are formed on the ITO layer 112 as metal layers for forming a drain bus line 106, and these metal layers are patterned. Consequently, a two-layered drain bus line is formed across the entire region by the drain bus line 106 and the drain electrode 107 in portions except for the intersections between the drain bus line 106 and the gate bus line 101 and by the drain bus line 106 and the ITO layer 112 in the intersections between the drain bus line 106 and the gate bus line 101.
In this prior art, however, metal film formation and patterning must be performed twice to form the drain electrode 107 and the drain bus line 106, and this complicates the fabrication process. Also, the drain bus line 106 and the drain electrode 107 are electrically connected through the contact hole b 114. Accordingly, if the connecting resistance in the interface between the drain bus line 106 and the drain electrode 107 increases due to variations in the fabrication process, the TFT does not normally operate any longer. This increases defects such as point defects. Furthermore, since the drain bus line 106 and the pixel electrode 110 are formed on the same layer, the problems of inability to increase the aperture ratio and easy occurrence of point defects remain unsolved.
In the TFT structure of Japanese Examined Patent Publication No. 4-52925 shown in FIGS. 3, 4A to 4F, and 5A to 5F, the drain bus line 106 and the pixel electrode 110 are formed on the same layer, and the drain bus line 106 cannot be located close to the pixel electrode 110 accordingly so the aperture ratio cannot be increased. Additionally, a metal foreign matter or a pattern residue formed when the drain bus line 106 or the pixel electrode 110 is patterned short-circuits the drain bus line 106 and the pixel electrode 110. This results in a point defect.
To solve these problems in Japanese Examined Patent Publication No. 4-52925, the TFT structure of Japanese Unexamined Patent Publication No. 6-130416 shown in FIGS. 6, 7A to 7F, and 8A to 8F includes the drain bus line 106 having a single-layered structure. Accordingly, when the drain bus line 106 at the intersection of the gate bus line 101 and the drain bus line 106 is etched, a solution such as ammonium ceric nitrate permeates from the step portion and etches the metal pattern of, e.g., Cr, or the drain bus line 106 cracks from the step portion. This results in a line defect which is a fatal defect for a liquid crystal display.
To solve the problems of the above two prior arts, in the TFT structure of Japanese Unexamined Patent Publication No. 1-105575 shown in FIGS. 9, 10A to 10G, and 11A to 11G, metal film formation and patterning must be performed twice to form the drain electrode 107 and the drain bus line 106, and this complicates the fabrication process. Also, the drain bus line 106 and the drain electrode 107 are electrically connected through the contact hole b 114. Accordingly, if the connecting resistance in the interface between the drain bus line 106 and the drain electrode 107 increases due to variations in the fabrication process, the TFT does not normally operate any longer. This increases defects such as point defects. Furthermore, since the drain bus line 106 and the pixel electrode 110 are formed on the same layer as in Japanese Examined Patent Publication No. 4-52925, the problems of inability to increase the aperture ratio and easy formation of point defects remain unsolved.